1. Field of the Invention
The present invention relates to a capacitive load driving circuit and a method of driving a capacitive load. More particularly, the present invention relates to a capacitive load driving circuit and a method of driving a capacitive load used for a capacitive load such as a liquid crystal display panel.
2. Description of Related Art
In a recent trend of thin flat panels, a size thereof has been increasingly growing. In the field of televisions in particular, even some liquid crystal panels have a size of over 50 inches. This tendency will be unchanged for some time in the future. However, a data line load of a TFT (Thin Film Transistor) is increasingly heavier as the size of the thin flat panel increases. This causes a problem that data writing cannot be performed up to the farthest end of a data line in one horizontal period (1 H period). To deal with this problem, in an output amplifier of a source driver (horizontal driver), effort has been made so far to increase a slew rate such that the data writing up to the farthest end of the data line (farthest end driving) can be performed in the 1 H period. However, a problem has arisen that power consumption of a source driver is increased and the chip temperature unusually gets high, when the output amplifier is designed such that the slew rate is appropriate to farthest end driving. To deal with the increase in the chip temperature, such measures may be taken as adding some changes to a tape on which a chip is provided in order to keep thermal resistance low, and applying a heat release tape to a chip. However, all of these lead to an increase in costs.
FIG. 1 is a block diagram showing a configuration example of a liquid crystal display device. The liquid crystal display device applies analog data signals generated based on digital video data to a liquid crystal panel. The liquid crystal display device includes a liquid crystal panel 1, a control circuit 2, a grayscale power supply circuit 3, a data line driving circuit (source driver) 4, and a scanning line driving circuit (gate driver) 5.
The liquid crystal panel 1 is a liquid crystal panel of an active matrix type with thin film transistors (TFTs) used as switch elements. In the liquid crystal panel 1, pixels are provided at regions corresponding to crossover points between n number (n is a natural number) of scanning lines 61 to 6n and m number (m is a natural number) of data lines 71 to 7m. The n number of scanning lines (gate lines) 61 to 6n are provided in the row direction with given spacing. The m number of data lines (source lines) 71 to 7m are provided in the column direction with given spacing. Therefore, the number of pixels in the entire display screen is n times m. Each pixel of the liquid crystal panel 1 includes a liquid crystal capacitance 8, a common electrode 9, and a TFT 10. The liquid crystal capacitance 8 is a capacitive load in terms of equivalence. The TFT drives a corresponding liquid crystal capacitance 8.
When the liquid crystal panel 1 is driven, a common potential Vcom is applied to the common electrode 9. Under this state, analog data signals generated based on digital video data are applied to the data lines 71 to 7m. In addition, a gate pulse generated based on a horizontal synchronizing signal, a vertical synchronizing signal and so forth, is applied to the scanning lines 61 to 6n. Consequently, characters, images and so forth are displayed on the display screen of the liquid crystal panel 1. As for color display, analog data red signals, analog data green signals, and analog data blue signals, which are generated based on red data, green data, and blue data of digital video data respectively, are applied to corresponding data lines. It means that operation is not directly affected just with data volume and circuitry being trebled. Therefore, the configuration and the operation with respect to the color display will not be explained here.
The control circuit 2 is composed of an ASIC (Application Specific Integrated Circuit) for example, and is supplied with a dot clock signal, a horizontal synchronizing signal and a vertical synchronizing signal, a data enable signal, and so forth, from the outside. Based on these input signals, the control circuit 2 generates control signals such as a strobe signal, a clock signal, a horizontal scanning pulse signal, a polarity signal, a vertical scanning pulse signal and so forth, to be supplied to the source driver 4 and the gate driver 5. The strobe signal is a signal with the same period as the horizontal synchronizing signal. The clock signal has an identical or different frequency in synchronization with the dot clock signal. The clock signal is used for example, to generate a sampling pulse from the horizontal scanning pulse signal, in a shift register included in the source driver 4. The horizontal scanning pulse signal is a signal with the same period as the horizontal synchronizing signal but delayed by several periods of the clock signal from the strobe signal. The polarity signal is inverted every one horizontal period, namely every one line, to drive the liquid crystal panel 1 in an alternate current manner. The polarity signal is also inverted every one vertical synchronizing period. The vertical scanning pulse signal is a signal with the same period as the vertical synchronizing signal.
The gate driver 5 sequentially generates a gate pulse in synchronization with timing of the vertical scanning pulse signal supplied from the control circuit 2. The gate driver 5 sequentially applies the generated gate pulse to the corresponding scanning lines 61 to 6n of the liquid crystal panel 1.
The grayscale power supply circuit 3 includes a plurality of resistances in a cascade connection between a reference voltage and ground, and a plurality of voltage followers with input nodes connected to connection points of adjacent resistances. The grayscale power supply circuit 3 amplifies grayscale voltages at the connection points of the adjacent resistances and supplies the amplified grayscale voltages to the source driver 4. The grayscale voltage is set for gamma transformation. Gamma transformation originally means to make correction to reverse a characteristic of a traditional image pickup tube, thereby restoring a normal video signal. Here, the gamma transformation corrects the analog video signal or the digital video data signal in order to obtain a reproduction image with fine grayscale, with the gamma of the entire system of the device being one (1). In general, gamma transformation is performed to an analog video signal or a digital video data signal for conformity to the characteristics of a CRT display, namely, to provide compatibility. Here, FIG. 2 is a graph showing an example of the relationship (gamma transformation characteristics) between 6-bit input data (given in hexadecimal (HEX)), and grayscale voltages V0 to V4 and V5 to V9.
As shown in FIG. 1, the source driver 4 includes a video data processing circuit 11, a digital-analog converter (DA converter) 12, and m number of output circuits 131 to 13m.
The video data processing circuit 11 includes a shift register, a data register, a latch circuit, and a level shifter (not shown). The shift register is a serial-in/parallel-out shift register composed of a plurality of delay flip-flops. The shift register performs shift operation to shift the horizontal scanning pulse signal supplied from the control circuit 2 in synchronization with the clock signal supplied from the control circuit 2, and outputs a multiple-bit parallel sampling pulse. The data register receives data of digital video data signals, which are supplied from the outside, as display data in synchronization with the sampling pulse supplied from the shift register, and supplies the display data to the latch circuit. The latch circuit receives the display data supplied from the data register in synchronization with a rising edge of the strobe signal supplied from the control circuit 2. The latch circuit retains the received display data until the next strobe signal is supplied, namely, during one horizontal period. The level shifter converts voltages of output data of the latch circuit and outputs the data as voltage-converged display data.
The DA converter 12 gives a grayscale property to which gamma correction has been made, to the voltage-converged display data supplied from the video data processing circuit 11 based on a set of grayscale voltages V0 to v4 or a set of grayscale voltages V5 to V9 supplied from the grayscale power supply circuit 3. The DA converter 12 converts correction data to which gamma correction has been made, into analog data signals and supplies the analog data signals to the corresponding output circuits 131 to 13m.
The output circuits 131 to 13m having the same configuration, are simply referred to as output circuit 13 when collectively mentioned. Similarly, the data lines (source lines) 71 to 7m are simply referred to as data line 7 when collectively mentioned. FIG. 3 is a circuit diagram showing a configuration example of the output circuit. The output circuit 13 includes voltage followers 141 and 142, and switches 151 and 152, and drives the data line 7.
The switch 151 is switched on when a polarity signal POL supplied from the control circuit 2 is “H” level and applies a positive-polarity data signal S supplied from the voltage follower 141 to the corresponding data line 7 of the liquid crystal panel 1. The switch 152 is switched on when the polarity signal POL supplied from the control circuit 2 is “L” level and applies a negative-polarity data signal S supplied from the voltage follower 142 to the corresponding data line 7 of the liquid crystal panel 1.
FIG. 4 is a circuit diagram showing a configuration example of the voltage follower 141. The voltage follower 141 includes a class A amplifier that includes N-channel MOS transistors MN1 and MN2, P-channel MOS transistors MP1 to MP3, constant current supplies CI1 and CI2, and a capacitor C1. The voltage follower 141 amplifies a positive-polarity data signal supplied from the corresponding DA converter 12 to an input node Vin and outputs the amplified data signal from an output node Vout.
FIG. 5 is a circuit diagram showing a configuration example of the voltage follower 142. The voltage follower 142 includes a class A amplifier that includes P-channel MOS transistors MP4 and MP5, N-channel MOS transistors MN3 to MN5, constant current supplies CI3 and CI4, and a capacitor C2. The voltage follower 142 amplifies a negative-polarity data signal supplied from the corresponding DA converter 12 to the input node Vin and outputs the amplified data signal from the output node Vout.
Next, an operation of the liquid crystal display device will be explained with reference to a timing chart. FIG. 6 is a view showing a timing chart of the operation of the liquid crystal display device. In FIG. 6, the period TF is one frame period and the period TH is one horizontal period. Here, a dot inversion driving method is employed as a driving method for driving the liquid crystal panel 1. That is to say, a polarity of a voltage applied to each of the data lines 71 to 7m is inverted every one dot (pixel) with respect to a common voltage Vcom applied to the common electrode 9. Generally, in a liquid crystal panel, continuously applying homopolar voltages to a liquid crystal cell causes a phenomenon called “burn-in” where traces of characters and so forth are left on a screen even after shutting off the electric power. The dot inversion driving method has been employed from the past to prevent “burn-in” of a liquid crystal panel. Usually, in a liquid crystal panel, a liquid crystal cell has approximately the same transmittance characteristic even when the polarity of the voltage applied to the liquid crystal cell is inverted. When using the inversion driving method therefore, it is general to use grayscale voltages with the identical voltage value both in the case of positive and negative polarities (positive-polarity and negative-polarity voltages having equal absolute values with respect to the common voltage Vcom).
A clock signal VCK indicated by (1) in FIG. 6 is a clock signal with the period TH used in the gate driver 5. The period TH is one horizontal period. The gate driver 5 sequentially generates gate pulses VG1, VG2, . . . , and VGn each one line in synchronization with pulses P1, P2, . . . , and Pn of the clock signal VCK respectively, as illustrated by (2) to (4) in FIG. 6 and sequentially applies the gate pulses VG1, VG2, . . . , and VGn to the scanning lines 61, 62, . . . , and 6n of the liquid crystal panel 1 respectively.
On the other hand, the source driver 4 outputs data signals from the output circuits 131, 132, . . . , and 13n to the data lines 71, 72, . . . , and 7n respectively, as illustrated by (5) and (6) in FIG. 6. Each of the data signals are outputted a few microseconds after each of the gate pulses VG1, VG2, . . . , and VGn are generated. A data signal VSeven illustrated by (5) in FIG. 6 shows a data signal outputted from even-numbered output circuits 13(2i) and a data signal VSodd illustrated by (6) in FIG. 6 shows a data signal outputted from odd-numbered output circuits 13(2i-1). That is, data signals VS2, VS4, . . . , and VS(2i) outputted from the output circuit 132, 134, . . . , and 13(2i) to the data lines 72, 74, . . . , and 7(2i) respectively, are referred to as the data signal VSeven when collectively mentioned. Similarly, data signals VS1, VS3, . . . , and VS(2i-1) outputted from the output circuits 131, 133, . . . , and 13(2i-1) to the data lines 71, 73, . . . , and 7(2i-1) respectively, are referred to as the data signal VSodd when collectively mentioned.
FIG. 7 is a view showing equivalent parasitic resistances and equivalent parasitic capacitances of the data lines of the liquid crystal panel 1 in the liquid crystal display device. Since the configuration of FIG. 7 corresponds to that of FIG. 1, the detail explanation will be omitted here. With reference to FIG. 7, the data line 7 of the liquid crystal panel 1 connected to the output circuit 13 of the source driver 4 can be represented as a distributed constant circuit of resistances and capacitances. The nearest and farthest points to the liquid crystal panel from the source driver 4 are referred to as a load near end and a load far end respectively. Here, the liquid crystal panel 1 includes panel load equivalent circuits 70 (701 to 70m) as the distributed constant circuits.
We have now discovered following facts. Slew rates of the amplifiers shown in FIGS. 4 and 5 are designed in accordance with worst-case conditions of loads driven by the amplifiers. That is to say, slew rates of the amplifiers are designed based on load conditions of the drive line (load far end) farthest away from the drive line (load near end) where the source driver 4 is positioned. In this case, load conditions are increasingly stricter as the size of the liquid crystal panel 1 served as a load becomes larger. When a slew rate is designed with an increase therein such that the slew rate is adapted to the above worst-case conditions, it is necessary to increase a differential stage bias current in the first stage of the amplifier. When the differential stage bias current is increased, a current of the output stage of the amplifier should also be increased accordingly. This is because a problem arises that a phase margin cannot be secured, unless a ratio of the current in the first stage to the current in the last stage is a certain value or above (e.g. fivefold). In this way, designing an amplifier with an increase in the slew rate may cause power consumption to increase and the temperature of a semiconductor chip to exceed the maximum temperature thereof.
Relevant to a capacitive load driving circuit used for a driver section, which is an output stage of a driving circuit in a liquid crystal display device (LCD), for example, a technique is disclosed in Japanese Laid-Open Patent Application JP-P2000-338461A (corresponding to U.S. Pat. No. 6,624,669B1). A driving circuit includes a level converting means, a first transistor, a first current controlling means, and a driving means. The level converting means performs level conversion of an input voltage into a first voltage. The first transistor receives the first voltage at a gate and outputs an output voltage based on the input voltage from a source. The first current controlling means controls a current that flows between the drain and source of the first transistor. The driving means makes the first transistor perform source follower operation.
As mentioned above, a driving circuit usable for a liquid crystal panel which is growing in size, requires that a slew rate should be increased based on load conditions, which may cause current consumption to be increased and the temperature of a semiconductor chip to exceed the maximum temperature thereof.